Lead Design Verification UCIe PHY IP Engineer

As a Lead Design Verification Engineer for UCIe PHY IP, you will play a crucial role in driving the execution of our project. Your responsibilities will include: - Leading internal DV team meetings by utilizing your expertise in functional verification fundamentals - Collaborating with RTL, AMS system modeling, and PD teams to define verification strategies - Designing verification environments and methodologies to enhance test plan creation, verification closure, RTL/GLS debug skills, formal verification, and PA simulation - Analyzing execution issues, developing new functional verification methodologies, and implementing them organization-wide Your strong background in SystemVerilog and UVM methodology, combined with previous experience in digital verification of serial bus multiprotocol PHY IPs (UCIe or SerDes IPs preferred), make you a perfect fit for this role. Qualifications required for this position: - B.E/B.Tech/M.E/M.Tech degree - Minimum of 5 years of experience in the field As a Lead Design Verification Engineer for UCIe PHY IP, you will play a crucial role in driving the execution of our project. Your responsibilities will include: - Leading internal DV team meetings by utilizing your expertise in functional verification fundamentals - Collaborating with RTL, AMS system modeling, and PD teams to define verification strategies - Designing verification environments and methodologies to enhance test plan creation, verification closure, RTL/GLS debug skills, formal verification, and PA simulation - Analyzing execution issues, developing new functional verification methodologies, and implementing them organization-wide Your strong background in SystemVerilog and UVM methodology, combined with previous experience in digital verification of serial bus multiprotocol PHY IPs (UCIe or SerDes IPs preferred), make you a perfect fit for this role. Qualifications required for this position: - B.E/B.Tech/M.E/M.Tech degree - Minimum of 5 years of experience in the field