FPGA
Skillathon
All India • 2 months ago
Experience: 2 to 6 Yrs
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Job Description
As a FPGA Physical Layer Developer for 5G-NR, you will be responsible for the following key tasks:
- Integrating FPGA IP Blocks using Xilinx Vivado Platform
- Demonstrating knowledge of AXI Protocols
- Implementing Xilinx PS-PL integration
- Programming in Verilog for RTL
- Developing FPGA Test Benches using Xilinx Vivado
- Implementing L1/Physical Layer on Xilinx FPGA (RFSoC)
- Utilizing FPGA Debugging Tools such as ILA, chipscope, VIO
- Utilizing engineering tools including Xilinx Vivado, Xilinx ISE/EDK
- Developing and testing FPGA Modem/Communication Blocks related to 4G/5G or other wireless standards
- Preference will be given to candidates with an M.Tech. in VLSI and a strong academic background
In addition to the responsibilities outlined above, it is recommended that candidates have experience with FPGA Modem/Communication Blocks development and testing related to 4G/5G or other wireless standards. Candidates with an M.Tech. in VLSI and a strong academic record will be given preference in the selection process. As a FPGA Physical Layer Developer for 5G-NR, you will be responsible for the following key tasks:
- Integrating FPGA IP Blocks using Xilinx Vivado Platform
- Demonstrating knowledge of AXI Protocols
- Implementing Xilinx PS-PL integration
- Programming in Verilog for RTL
- Developing FPGA Test Benches using Xilinx Vivado
- Implementing L1/Physical Layer on Xilinx FPGA (RFSoC)
- Utilizing FPGA Debugging Tools such as ILA, chipscope, VIO
- Utilizing engineering tools including Xilinx Vivado, Xilinx ISE/EDK
- Developing and testing FPGA Modem/Communication Blocks related to 4G/5G or other wireless standards
- Preference will be given to candidates with an M.Tech. in VLSI and a strong academic background
In addition to the responsibilities outlined above, it is recommended that candidates have experience with FPGA Modem/Communication Blocks development and testing related to 4G/5G or other wireless standards. Candidates with an M.Tech. in VLSI and a strong academic record will be given preference in the selection process.
Skills Required
chipscope
VIO
FPGA IP Blocks integration using Xilinx Vivado Platform
Knowledge on AXI Protocols
Xilinx PSPL integration knowledge
RTL Programming Verilog
FPGA Test Bench Development using Xilinx Vivado
L1Physical Layer Implementation on Xilinx FPGA RFSoC
FPGA Debugging Tools Experience ILA
Working knowledge of the following engineering tools Xilinx Vivado
Xilinx ISEEDK
FPGA ModemCommunication Blocks developmenttesting experience regarding 4G5G
any wireless standard will be preferred
MTech in VLSI will be preferred
Good Academic Score
Posted on: March 3, 2026
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