Sr. Staff RTL Engineer

Job Description As a highly motivated Senior Staff design engineer at Lattice Semiconductor, your primary responsibility will be the design and development of RTL for a Machine Learning engine. Your role involves efficiently implementing ML operators using resources on low power FPGA. It is essential to have experience in optimizing data paths for high throughput and low latency. Additionally, a good understanding of neural network accelerators and/or DSP processors is crucial for success in this position. Key Responsibilities - In-depth experience in designing and developing RTL using Verilog, System Verilog-HDL. - Ability to conduct functional simulation using industry standard simulation tools such as Xcelium-Cadence, VCS-Synopsys. - Architect and design RTL for Machine Learning compute engines targeting low-power FPGA platforms. - Experience in optimizing memory bandwidth, data reuse, pipeline design, and parallelism. - Proven track record of designing data paths for high-throughput, low-latency applications. - Deep understanding of machine learning, data models to optimally map it with hardware. - Proficiency in performance analysis and hardware profiling techniques. - Strong grasp of numerical formats (FP16, INT8, INT4, fixed-point arithmetic) and associated costs for hardware implementation. - Familiarity with FPGA/ASIC synthesis flow, timing closure. - Working knowledge of computer architecture and memory management. - Experience with C and/or SystemC is considered a plus. Qualifications Required - BE/MTech/PhD in Electronics, Electrical or Computer Engineering. - Minimum of 14 years of experience in RTL design (12 years for MTech and 8 years for PhD). - Independent and self-motivated with the ability to execute under dynamic environments and uncertainties. - Innovative problem solver with a penchant for devising newer and better solutions for existing problems. - Strong cross-team communication skills and proficiency in technical documentation are desired. Job Description As a highly motivated Senior Staff design engineer at Lattice Semiconductor, your primary responsibility will be the design and development of RTL for a Machine Learning engine. Your role involves efficiently implementing ML operators using resources on low power FPGA. It is essential to have experience in optimizing data paths for high throughput and low latency. Additionally, a good understanding of neural network accelerators and/or DSP processors is crucial for success in this position. Key Responsibilities - In-depth experience in designing and developing RTL using Verilog, System Verilog-HDL. - Ability to conduct functional simulation using industry standard simulation tools such as Xcelium-Cadence, VCS-Synopsys. - Architect and design RTL for Machine Learning compute engines targeting low-power FPGA platforms. - Experience in optimizing memory bandwidth, data reuse, pipeline design, and parallelism. - Proven track record of designing data paths for high-throughput, low-latency applications. - Deep understanding of machine learning, data models to optimally map it with hardware. - Proficiency in performance analysis and hardware profiling techniques. - Strong grasp of numerical formats (FP16, INT8, INT4, fixed-point arithmetic) and associated costs for hardware implementation. - Familiarity with FPGA/ASIC synthesis flow, timing closure. - Working knowledge of computer architecture and memory management. - Experience with C and/or SystemC is considered a plus. Qualifications Required - BE/MTech/PhD in Electronics, Electrical or Computer Engineering. - Minimum of 14 years of experience in RTL design (12 years for MTech and 8 years for PhD). - Independent and self-motivated with the ability to execute under dynamic environments and uncertainties. - Innovative problem solver with a penchant for devising newer and better solutions for existing problems. - Strong cross-team communication skills and proficiency in technical documentation are desired.